Semiconductor device having silicon carbide and conductive pathway interface

ABSTRACT

The present invention provides an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of co-pending U.S. patentapplication Ser. No. 10/655,438, filed Sep. 4, 2003, which is acontinuation of U.S. patent application Ser. No. 10/013,182, filed Dec.7, 2001, which is a divisional of U.S. patent application Ser. No.09/365,129, filed Jul. 30, 1999, which is a continuation-in-part of U.S.patent application Ser. No. 09/193,920, filed Nov. 17, 1998, all ofwhich are hereby incorporated by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the fabrication of integratedcircuits on substrates. More particularly, the invention relates to amethod of reducing oxides on a substrate prior to depositing a layerthereover in the fabrication process.

2. Background of the Invention

Reliably producing sub-half micron and smaller features is one of thekey technologies for the next generation of very large scale integration(VLSI) and ultra large scale integration (ULSI) integrated circuits.However, as the fringes of circuit technology are pressed, the shrinkingdimensions of interconnects in VLSI and ULSI technology has placedadditional demands on the processing capabilities. The multilevelinterconnects that lie at the heart of this technology require carefulprocessing of high aspect ratio features, such as vias and otherinterconnects. Reliable formation of these interconnects is veryimportant to the VLSI and ULSI success and to the continued effort toincrease circuit density and quality of individual substrates and die.

Conventional chemical vapor deposition (CVD) and physical vapordeposition (PVD), and now electroplating, techniques are used to depositelectrically conductive material into the contacts, vias, lines, orother features formed on the substrate. Considerable effort has focusedon reliably depositing material in these high aspect ratio, smallerinterconnects.

One issue that still needs improvement as feature sizes shrink is thereduction of oxides in these very small features. FIG. 1 shows asubstrate 2 with a via 4 formed within an electrically insulative ordielectric layer 6. With current technology, the aspect ratio hasincreased to approximately 5:1 for the height to width ratio, shown inFIG. 1 as x with respect to d. As a result, it is becoming moredifficult to properly prepare the surfaces within the small features forsubsequent processing, especially in the lower interconnect portions,such as in the interconnect areas 8, 9.

In part, this attention to improved cleaning is due to a desired changein the conductor metal. For example, copper is now being considered asan interconnect material in place of aluminum, because copper has alower resistivity (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum) andhigher current carrying capacity. However, copper is highly susceptibleto oxidation. With copper depositions, oxidation is considered adetriment and interferes with adhesion on the adjacent layer, affectsconductivity of the copper feature, and reduces the reliability of theoverall circuit. Furthermore, present processes utilize oxygen for avariety of reasons in some instances and in other instances, oxygen is abyproduct of the reactions. Thus, even carefully controlled environmentsmay contain oxygen that may oxidize copper or other conductivematerials, such as aluminum, to the detriment of the circuit.

Copper has other difficulties. Because copper is difficult to etch in aprecise pattern, traditional deposition/etch processes for forminginterconnects has become unworkable, and accordingly, a “dual damascene”structure is being used for copper interconnects. In a typical dualdamascene structure, the dielectric layer is etched to define both thecontacts/vias and the interconnect lines. Metal is then inlaid into thedefined pattern and any excess metal is typically removed from the topof the structure in a planarization process, such as CMP. This complexapproach increases the importance of obtaining properly cleaned surfaceswithin the interconnects.

Prior to the present invention, an inert gas plasma, such as an Argon(Ar) plasma, physically cleaned the surfaces of interconnects and metallayers, such as aluminum and copper, as ions were attracted to thesubstrate surface to physically bombard the surface and remove thesurface of the uppermost layer. However, the Ar ions in the plasmadepend on directionality to clean and with the decreasing sizes of theinterconnects, the increasing aspect ratios, and the resulting shadingthat can occur, this process is ineffective in removing oxides in thesmall features.

Therefore, there is a need for an improved cleaning process to reduceoxides formed on the surface of substrates and materials depositedthereon.

SUMMARY OF THE INVENTION

The present invention provides a process for removing oxides and othercontaminants comprising initiating a plasma containing a reducing agentin a chamber and exposing at least a portion of a substrate surfacehaving a reducible contaminant to the reducing agent. In a preferredembodiment, the reducing agent comprises a compound containing nitrogenand hydrogen, preferably ammonia. One example may include introducing areducing agent comprising nitrogen and hydrogen into a chamber,initiating a plasma in the chamber, and exposing an oxide to thereducing agent. The plasma process parameters to reduce an oxide, suchas copper oxide, using ammonia include a pressure range of about 1 toabout 9 mTorr, an RF power of about 100 to about 1000 watts for a 200 mmwafer to the chamber with a power density of about 1.43 to 14.3watts/cm², a substrate temperature of about 100° to about 450° C., ashowerhead to substrate spacing of about 200 to about 600 mils, and areducing agent flow rate of about 100 to about 1000 sccm.

An exemplary process sequence of the invention, such as for forming adual damascene structure, includes depositing a dielectric on asubstrate, depositing an etch stop, etching the etch stop, depositing abarrier layer, depositing a metal layer, initiating a reducing agentplasma, reducing oxides which may form on at least some of the metalsurface with the reducing agent, such as ammonia, and in situ depositinga layer, such as a nitride layer, over the reduced surface.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features, advantages andobjects of the present invention are attained and can be understood indetail, a more particular description of the invention, brieflysummarized above, may be had by reference to the embodiments thereofwhich are illustrated in the appended drawings.

It is to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 shows a schematic of a multilevel substrate with interconnects;

FIG. 2 is a flow chart of one example of a deposition/etching processusing the plasma reducing process;

FIG. 3 is a graph of dielectric compatibility showing oxygen levelsobtained from a copper wafer after a CMP process;

FIG. 4 is a graph in comparison to FIG. 3 showing an improvement by theplasma reducing process of the present invention, having decreasedoxygen levels;

FIG. 5 shows a cross-sectional view of one commercially available CVDplasma reactor in which the plasma reducing process of the presentinvention may be performed;

FIG. 6 is a dual damascene structure showing an oxide layer on aconductor; and

FIG. 7 is a dual damascene structure with a layer deposited on thecleaned conductor.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The present invention provides a process for removing oxides and othercontaminants comprising initiating a plasma containing a reducing agentand exposing at least a portion of a substrate surface having areducible contaminant to the plasma and the reducing agent. The reducingprocess is believed to increase the adhesion of the adjoining layer andto decrease the electrical resistance of the combined layers bydecreasing the oxygen content in the oxidized layer. At least in part,these adverse oxide effects are believed to be due to the metal oxides,such as copper oxide (Cu₂O), reducing the mobility of the metal, e.g.,copper (Cu). In the preferred embodiment, the process is performed insitu to minimize re-contamination before the deposition of a subsequentlayer. In situ processing may be particularly important with copper,because of its rapid susceptibility to oxidation.

In an integrated circuit (IC) fabrication, a metal layer is deposited atsome point in the deposition process and typically comprises aluminum orcopper. Because copper is being considered for the conducting material,much of the discussion herein is addressed to copper. However, thepresent invention may be used for any oxidized metal layers, such as Ti,TiN, Ta, TaN, Al, and others. It may also be used for other layers,including silicon oxides. The present invention combines the chemicalreactive cleaning of a reducing agent, such as a compound containingnitrogen and hydrogen, including ammonia, with the physical bombardmentof the ions from a plasma, and so may be used on a variety of materialsto effectuate the reduction of contaminants, such as oxides. Whileoxides are clearly discussed in the specification, other contaminantswould fall within the scope of the present invention. It is believedthat the nitrogen combined with hydrogen allows a reduced energy levelto break the hydrogen bonds and otherwise disassociate the molecules andmore effectively utilize the reducing agent to clean the contaminants.

Before depositing a layer over the metal, such as a nitride, the metalis cleaned according to the teaching of the present invention. By“cleaning”, the term is meant to include a reduction of an oxide orother contaminants. Cleaning may be necessary due to exposure to anoxygen source (such as air, diatomic oxygen, or oxygen contained in amolecular compound). This cleaning may take place in the same CVD orplasma enhanced chemical vapor deposition (“PECVD”) chamber in which thesubsequent layer is deposited, as an in situ process. The term “in situ”is intended to include in a given chamber, such as in a plasma chamber,or in a system, such as an integrated cluster tool arrangement, withoutexposing the material to intervening contamination environments. An insitu process typically minimizes process time and possible contaminantscompared to relocating the substrate to other processing chambers orareas.

In one embodiment, the reduction process typically includes introducingthe reducing agent, such as ammonia, into a vacuum chamber andinitiating a plasma where the plasma excites the ammonia into anenergized ionic state. The energized ions chemically react with theoxide and the oxides are removed according to the following equation:3 Cu₂O+2 NH₃→6 Cu+3 H₂O+N₂The plasma provides the energy necessary to disassociate the ammonia andto provide the desired ion bombardment. The ionized particles impact theoxidized surfaces in the reduction process to further enhance thecleaning. The combination of chemical reactions and physical bombardmentof ions increases the likelihood that all surfaces in small features arecleaned or oxides reduced.

The process of the invention is believed to afford at least twoadvantages. First, the cleaned surface is better prepared for increasedadhesion to an adjoining layer. Removal of the oxide allows a betterbond to the base conducting material. Secondly, oxides are known toincrease resistance of a layer or combined layers. Thus, the reductionof the oxide decreases the resistance or impedance of the combinedlayers.

The plasma process parameters for at least one embodiment, using ammoniato reduce the copper oxide, include a pressure range of about 1 to about9 mTorr, an RF power of about 100 to about 1000 watts to a chamber, thatmay have a reaction zone, to create the plasma having a power density ofabout 1.43 to about 14.3 watts/cm², a substrate surface temperature ofabout 100° to about 450° C., a showerhead to substrate spacing of about200 to about 600 mils, and a reducing agent flowing at a rate of about100 to about 1000 sccm into the chamber. The gas dispersion element,such as a “showerhead”, is commonly known to those with ordinary skillin the art and is used interchangeably herein, and includes other gasdispersion elements. The “reaction zone” is the zone between theshowerhead and the substrate surface in the chamber, such as one in aCENTURA DxZ™ CVD reactor, fabricated and sold by Applied Materials, Inc.of Santa Clara, Calif.

A preferred process range includes a pressure range of about 3 to about7 mTorr, an RF power of about 100 to about 500 watts for a 200 mm waferhaving a power density of about 1.43 to about 7.14 watts/cm², asubstrate temperature of about 200° to about 400° C., a showerhead tosubstrate spacing of about 200 to about 500 mils, and a reducing agentflowing at a rate of about 100 to about 500 sccm. A most preferredprocess range includes a pressure range of about 4 to about 6 mTorr, anRF power of about 200 to about 400 watts having a power density of about2.86 to about 5.72 watts/cm², a substrate temperature of about 300° toabout 400° C., a showerhead to substrate spacing of about 300 to about400 mils, and a reducing agent flowing at a rate of about 200 to about300 sccm. Additionally, carrier gases may be used in conjunction withthe above process parameters to assist in stabilizing the gas flow andthe plasma reaction. The flow rate of the carrier gases, such as helium,argon, and nitrogen, could be approximately 0 to 2000 sccm.

The plasma reducing process reduces, treats, or otherwise modifies thesurface in about 5 to about 60 seconds. Preferably, the ammonia plasmais generated in one or more treatment cycles and purged between cycles.However, in most cases, one treatment cycle lasting 10 secondseffectively removes oxygen from an oxidized copper surface. Naturally,the parameters could be adjusted for other materials besides copper andother contaminants besides oxides.

FIG. 2 shows a deposition/plasma reducing sequence of one example of thepresent invention. Other sequences, fabrication techniques, andprocesses may be used. Typically, a dielectric such as silicon dioxide,silicon nitride, or silicon carbide is deposited on a substrate. Theterm “substrate” herein includes the IC base or the IC includingdeposited materials or levels thereon, as the context may indicate. Anetch stop is deposited over the dielectric and interconnects are etchedtherethrough to form a pattern. Horizontal interconnects are typicallyreferred to as lines and vertical interconnects are typically referredto as contacts or vias; contacts extend to a device on the underlyingsubstrate, while vias extend to an underlying metal layer, such as M1,M2, etc. Once the lines and contacts/vias are patterned, such as shownin FIG. 1, a barrier layer, such as a TiN layer, is deposited over thepattern to restrict the diffusion of the conductor into the dielectriclayer(s). The conducting material may then be deposited over the barrierlayer. An oxidation may form on the conducting material, impedingadhesion and conductance. The substrate may be placed in a processingchamber for plasma cleaning that may be in situ with prior or subsequentprocesses. Typically, the system would initiate a plasma and introduce areducing agent into the chamber, whereupon the plasma cleaning wouldoccur. The plasma would assist in energizing the reducing agentmolecules to clean and otherwise reduce the oxide.

After the conductor is cleaned, another layer, such as a nitride, may bein situ deposited over the conductor to reduce further contaminationfrom an adverse environment, such as one with oxygen. Typically, thislayer is a dielectric layer, but can include other types of layers, suchas a barrier layer, an etch stop, or a passivation layer. Alternatively,the reduced substrate may be transported to a different chamber forsubsequent processing. The cleaning is not restricted to theconductor—other layers before and after the conductor layer could beplasma cleaned using the underlying concepts of the present invention.

EXAMPLE 1 Without an Ammonia Plasma Reducing Process

FIG. 3 shows the oxygen detected through a 500 Å nitride layer depositedon a copper surface after a CMP process without a plasma reducingprocess. The x-axis represents the binding energy in electron volts(ev), the y-axis represents counts per signal (c/s), and the z-axisrepresents a relative depth profile through the nitride film layer. Thex-axis, showing the binding energy, is element specific and thesubstrate layers have been tested at an oxygen binding energy level todetect its presence. The y-axis represents the oxygen level detected atan oxygen-specific binding energy. Because the z-axis is relative, thedistance between the two largest peaks along the z-axis is theapproximate thickness of the 500 Å nitride layer. Beyond the 500 Ånitride layer, the signal count drops to approximately zero becausecopper is a conductor. FIG. 3 shows a first high peak closest to theorigin of the z-axis of ˜11000 c/s. This first and highest peakrepresents the surface of the nitride layer and may be ignored for thepresent purposes. The last large peak at a depth of ˜500 Å representsthe oxygen level of ˜6000 c/s at the nitride/copper interface. Thisinterface has a quantity of copper oxide that has not been reduced inaccordance with the teaching of the present invention.

EXAMPLE 2 With an Ammonia Plasma Reducing Process

FIG. 4 is a graph corresponding to FIG. 3, showing the results from anexemplary copper surface substrate treated by an ammonia plasma reducingprocess of the present invention. FIG. 4 can be compared to FIG. 3 andthe axes represent similar scales and values. Similar to the substratesurface of FIG. 3, a 500 Å nitride layer was deposited on the copperafter applying the plasma reducing process of the present invention.FIG. 4 shows an overall lower oxygen level beyond the initial surfacepeak, where the initial surface peak may again be ignored for thepresent purposes. Noticeably, the oxygen level at the nitride/copperinterface, represented by the second peak at a depth of about 500 Å, hasbeen lowered to a level of ˜3000 c/s due to the elimination or reductionof the oxide from the copper surface.

FIG. 5 is a cross-sectional view of a CVD plasma reactor in which theabove plasma reducing process may be performed, such as a CENTURA DxZ™mentioned above. The present invention could be used in other reactors,such as a lamp heated reactor. Reactor 10 contains a gas distributionmanifold 11, which may be the above described showerhead, for dispersingprocess gases through perforated holes (not shown) in the manifold to asubstrate or wafer 16 that rests on a substrate support plate orsusceptor 12. Susceptor 12 is resistivity heated and is mounted on asupport stem 13, so that susceptor 12 and the wafer supported on theupper surface of susceptor 12 can be controllably moved by a lift motor14 between a lower loading/off-loading position and an upper processingposition, which is spaced closely adjacent to the manifold 11. Whensusceptor 12 and the wafer 16 are in the processing position, they aresurrounded by an insulator ring 17. During processing, gases inlet tomanifold 11 are uniformly distributed radially across the substratesurface. The gases exhaust through a port 24 by a vacuum pump system 32.

The deposition process performed in reactor 10 can be either a thermalprocess or a plasma enhanced process. In a plasma process, a controlledplasma is formed adjacent to the wafer by RF energy applied todistribution manifold 11 from RF power supply 25 with susceptor 12grounded. Gas distribution manifold 11 is also an RF electrode, whilesusceptor 12 is grounded. RF power supply 25 can supply either single ormixed frequency RF power to manifold 11 to enhance the decomposition ofany reactive species introduced into chamber 15. A mixed frequency RFpower supply typically supplies power at a high RF frequency (RF1) of13.56 MHz and at a low RF frequency (RF2) of 350 kHz. The systemcontroller 34 and memory 38 control the activities of the CVD reactor.An example of such a CVD reactor is described in U.S. Pat. No.5,000,113, which is incorporated by reference and entitled “ThermalCVD/PECVD Reactor and Use for Thermal Chemical Vapor Deposition ofSilicon Dioxide and In-situ Multi-step Planarized Process,” issued toWang et al. and assigned to Applied Materials, Inc., the assignee of thepresent invention.

With the present invention, the above chamber can be used to plasmareduce an oxide with a reducing agent and particularly a copper oxidewith ammonia. The reducing agent can be introduced through manifold 11and be uniformly distributed radially across the wafer surface for theplasma reducing process in the manner described above, followed by thegases exhausting through the port 24.

The above discussion applies in general to the improvement provided bythe plasma reducing process and can be used in multiple environments, onsubstrates, and in a variety of processes. This plasma reducing processhas particular applicability to the increased density and complexity ofa dual damascene structure. The following discussion briefly discussesaspects from a dual damascene structure and how the plasma reducingprocess may be utilized.

FIGS. 6 and 7 represent a dual damascene structure which can be cleanedusing the techniques of the present invention. In forming one type ofdual damascene structure, a first dielectric layer 30 is deposited on asubstrate 32, followed by an etch stop 34 deposition. The etch stop ispattern etched to define contact/via openings 40 and to expose the firstdielectric layer in the areas where the contacts/vias are to be formed.A second dielectric layer 38 is deposited over the etch stop andpatterned to define interconnect lines, preferably using conventionalphotolithography processes with a photoresist layer, as would be knownto those with ordinary skill in the art. The interconnects andcontacts/vias are then etched using reactive ion etching or otheranisotropic etching techniques and any photoresist or other materialused to pattern the layers is removed using an oxygen strip or othersuitable process. A barrier layer 44 is then preferably depositedconformally in the metallization pattern to prevent metal migration intothe surrounding silicon and/or dielectric material.

With the present invention, the above plasma reducing process may beuseful on the barrier layer or other layers deposited prior orsubsequent to the metal layer. The regime and parameters discussed abovefor the plasma reduction of the conductor could be adjusted for theparticular layer in question.

The metal layer 47 is deposited in the vias and lines and is preferablya conductive material such as aluminum, copper, tungsten or combinationsthereof with the recent trend being copper. The metal layer is depositedusing either CVD, PVD, electroplating, or combinations thereof to formthe conductive structure. Once the structure has been filled with copperor other metal, a CMP process may be used to planarize the metalsurface. In other embodiments, a sacrificial layer may be deposited onthe field areas between the interconnects prior to the metal deposition,and then the sacrificial layer stripped after the metal is deposited,leaving a surface suitable for the next stage of the deposition process.The structure surface may be planarized, using a CMP process at thisstage and/or at other stages. The above plasma reducing process may beinitiated to remove or reduce a contaminant layer 48, such as copperoxide, that may have formed on the metal layer 47, including theinterconnects 46. In the preferred embodiment, the plasma reducingprocess is applied in situ with the deposit of the adjoining layer 50,shown in FIG. 7. This layer may be another dielectric layer, a barrierlayer, a passivation layer, or some other layer beside the metal layer.

Specifically, the process steps could include: depositing a firstdielectric layer, such as a fluorinated silicate glass (FSG) layer, on asubstrate, depositing a low k dielectric etch stop on the firstdielectric layer, patterning the etch stops to define the contacts/vias,stripping the patterning medium such as a photoresist layer, depositinga second dielectric layer, such as an FSG layer, and patterning a resistlayer on the second dielectric layer to define one or moreinterconnects. Once the dual damascene structure has been formed, theprocess can include: depositing a barrier layer in the structure,depositing a metal layer such as copper, and exposing an oxidizedsurface of the metal layer to a plasma with the reducing agent to reducethe oxide. Another layer, such as a nitride, may then be deposited overthe surface in situ with the reducing process.

While the foregoing is directed to the preferred embodiment of thepresent invention, other and further embodiments of the invention may bedevised without departing from the basis scope thereof, and the scopethereof is determined by the claims that follow. Furthermore, in thisspecification, including particularly the claims, the use of“comprising” with “a” or “the”, and variations thereof means that theitem(s) or list(s) referenced includes at least the enumerated item(s)or list(s) and furthermore may include a plurality of the enumerateditem(s) or list(s), unless otherwise stated.

1. A semiconductor device comprising: an interface defined by a firstinsulating layer comprising silicon carbide and one or more conductivepathways disposed within said layer, the interface having oxidationreduced portions; and a second insulating layer disposed upon saidinterface coincident with removal of said oxidation reduced portions. 2.The semiconductor device of claim 1 wherein the second insulating layercomprises at least one layer selected from the group consisting of apatterned etch stop layer, a barrier layer, and a film comprisingsilicon carbide.
 3. The semiconductor device of claim 1 wherein theconductive pathways are formed from at least one of copper, titanium,tantalum, and tungsten.
 4. A semiconductor device comprising: aninterface defined by a first insulating layer and one or more conductivepathways disposed within said layer, the interface having oxidationreduced portions; and a second insulating layer comprising siliconcarbide disposed upon said interface coincident with removal of saidoxidation reduced portions.
 5. A semiconductor device interfacecomprising: a layer comprising silicon carbide; one or more conductivedevices disposed within said layer, said layer and conductive devicesdefining said interface, wherein said interface is treated with acontinuous plasma treatment to remove oxidation and deposit a secondlayer thereupon.
 6. The semiconductor device interface of claim 5wherein the conductive devices are formed from at least one of copper,titanium, tantalum, and tungsten.